Projects

prisc — Portable Risc-V Instruction Set Cimulator

This project began as a rewrite of a computer architecture assignment. The original assignment was a "full" simulation of an unprivileged Risc-V system with RV64I and RV64F. The current state-of-affairs for this project is a mostly working simulation of the unprivileged RV64I, RVI64E, RV32I, and RV32E base integer ISAs.

Status: Work in progress.

Source: https://sr.ht/~izak8/prisc/